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Universal Chiplet Interconnect Express (UCIe) Controller
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The IP also enables latency-optimized NoC-to-NoC links with streaming protocols.
The controller IP implements a RDI interface to the PHY and a FDI interface between the Die-to-Die Adapter layer and Protocol layer. These interfaces include all the necessary sideband signaling for protocol discovery and negotiation between two dies and smooth link initialization and operation.
Synopsys UCIe Controller IP offers maximum performance, minimum latency and implementation flexibility. The IP ensures link reliability by supporting retry mechanism and performing CRC or parity checks for error detection.
The flexible IP implementation targets single module or multi-module configurations, both for advanced and standard packages.
Synopsys UCIe Controller IP interoperates with Synopsys UCIe PHY to provide a complete, low-latency die-to-die interface solution that is optimized for bandwidth, power and area.
The controller IP implements a RDI interface to the PHY and a FDI interface between the Die-to-Die Adapter layer and Protocol layer. These interfaces include all the necessary sideband signaling for protocol discovery and negotiation between two dies and smooth link initialization and operation.
Synopsys UCIe Controller IP offers maximum performance, minimum latency and implementation flexibility. The IP ensures link reliability by supporting retry mechanism and performing CRC or parity checks for error detection.
The flexible IP implementation targets single module or multi-module configurations, both for advanced and standard packages.
Synopsys UCIe Controller IP interoperates with Synopsys UCIe PHY to provide a complete, low-latency die-to-die interface solution that is optimized for bandwidth, power and area.
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