You are here:
UMC L28HPC+LVT 28nm Deskew PLL - 900MHz-4500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.
特色
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
可交付内容
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
查看 UMC L28HPC+LVT 28nm Deskew PLL - 900MHz-4500MHz 详细介绍：
- 查看 UMC L28HPC+LVT 28nm Deskew PLL - 900MHz-4500MHz 完整数据手册
- 联系 UMC L28HPC+LVT 28nm Deskew PLL - 900MHz-4500MHz 供应商