MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
You are here:
UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library
UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library
查看 UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library 详细介绍：
- 查看 UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library 完整数据手册
- 联系 UMC 55nm e-flash Logic Process , 3.3V Analog ESD IO cell Library 供应商
Logic Libraries IP
- Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
- Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)
- Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)
- SMIC 0.13um Low Leakage UHD RVT_x000D_ Logic standard cell library, compatible with E-Flash and EEPROM process.