MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.
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