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UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
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Interface Solution
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Interlaken Protocol IP (High Speed Chip-To-Chip Interface)
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
- Common Public Radio Interface (CPRI) v.7.0 IPC
- Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- Common Public Radio Interface (CPRI) v.6.1 IPC