MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
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UltraScale Integrated 100G Ethernet MAC/PCS
Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PCS) core for high performance applications. The core is designed to the IEEE 802.3-2012 specification in the latest Virtex® UltraScale™ and Kintex® UltraScale FPGAs.
The Xilinx 100 Gbps Ethernet MAC and PCS core provides high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The PCS portion of the IP can be configured in CAUI-10 (10 lanes x 10.3125G), CAUI-4 (4 lanes x 25.78125G) or a dynamically switchable CAUI-10 and CAUI-4 mode.
The Xilinx 100 Gbps Ethernet MAC and PCS core provides high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The PCS portion of the IP can be configured in CAUI-10 (10 lanes x 10.3125G), CAUI-4 (4 lanes x 25.78125G) or a dynamically switchable CAUI-10 and CAUI-4 mode.
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