Ultra low power C-programmable DSP core
NXP distributes the CoolFlux DSP core through its corporate Innovation & Technology (I&T) division with license support of NXP's Intellectual Property & Licensing Department (IP&L).
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Block Diagram of the Ultra low power C-programmable DSP core

synthesizable IP
- 2D Graphics Processor for Wearables/IoT
- I3C Slave
- TFT/LCD/MIPI Display Controller and Composition Engine
- High Throughput and Low Latency Data Compression Engine
- Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process
- Frequency Synthesizable PLL (Vcc=1.8V, Fin=10~40MHz, Fout=200~500MHz, Jitter= +/- 120pS)