NXP has introduced a new embedded DSP core for ultra low power applications. Based on many years of experience in the design of ultra low power electronics, the core has been developed and is in use for baseband signal processing such as in software defined radios. Targeted products include WiMAX, satellite radio, digital receivers, Bluetooth, Zigbee, cable modems, etc. CoolFlux BSP is at C-code level backwards compatible with CoolFlux DSP software and adds efficient complex arithmetic and SIMD acceleration.
NXP distributes the CoolFlux BSP core through its corporate Innovation & Technology (I&T) division with license support of NXP's Intellectual Property & Licensing Department (IP&L).
- Ultra low power consumption
- 31 µW/MHz @ 0.8 V (65 nm CMOS)
- 70 µW/MHz @ 1.2 V (65 nm CMOS)
- 40 µW/MHz @ 0.8 V (90 nm CMOS)
- 90 µW/MHz @ 1.2 V (90 nm CMOS)
- 53 µW/MHz @ 0.8 V (130 nm CMOS)
- 120 µW/MHz @ 1.2 V (130 nm CMOS)
- 390 µW/MHz @ 1.8 V in (180 nm CMOS)
- Highly optimizing C-compiler software toolkit
- Minimal core size (65k gates), excluding debug interface (6k gates)
- Small memory footprint
- Performance (Worst Case Commercial Conditions, standard VT)
- 150 MHz @ 1.8 V 180 nm CMOS
- 190 MHz @ 1.2 V 130 nm CMOS
- 245 MHz @ 1.2 V 90 nm CMOS
- 300 MHz @ 1.2 V 65 nm CMOS (>5000 MOPS peak)
- A library of building blocks for complex arithmetic, SIMD acceleration, FFT and modem functions is available.
- The CoolFlux BSP is available on FPGA board for testing and analyzing. Or you can evaluate the CoolFlux using the software toolkit.
Block Diagram of the Ultra low power C-programmable Baseband Signal Processor core