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Ultra-low-power 12-bit SAR ADC with lowest voltage
This ultra-low-power 12-bit ADC IP is a general purpose Analog to Digital Converter (ADC) for low-power applications based on successive approximation register architecture with a core sampling frequency ranging from 100 KS/s up to 1 MS/s. The ultra-low power is achieved by employing an advanced comparator based on the bulk biasing principle. Therefore, only dynamic current is consumed and the power consumption is fully proportional to the sampling rate.
This ADC IP features an outstanding dynamic performance that includes 66 dB SNR, -72 dB THD, and 10.5-bit ENOBs. The obtained figure of merit is only 16 fJ/Sampling rate/Conv-step for a sampling frequency of 1 MS/s excluding references.
This ADC IP features an outstanding dynamic performance that includes 66 dB SNR, -72 dB THD, and 10.5-bit ENOBs. The obtained figure of merit is only 16 fJ/Sampling rate/Conv-step for a sampling frequency of 1 MS/s excluding references.
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Block Diagram of the Ultra-low-power 12-bit SAR ADC with lowest voltage
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