Ultra Low Power 10b 100kS/s ADC
SAR AD converter designed on the ST 65 LP technology. It
consumes 600nW on silicon, reaching an energy efficiency of
12.5fJ/conversion-step.
特色
- - 600nW consumption during operation
- - Power-down consumption of 10nW
- - 0.037mm² area
- - Comparator auto-calibration
- - 20mV/V gain error and 1mV offset typical
- - 55.3dB SNDR
- - 62.6dB SFDR
- - 1.1 INL and 2.3 DNL
- - 1kHz ERBW
优势
- -
可交付内容
- - GDS II layouts
- - LEF abstracts
- - CDL netlists
- - Liberty timings
- - Verilog description
- - A full datasheet
- - An integration note
应用
- - Ultra-low power sensor interface
- - Autonomous sensor network nodes
- - Battery powered systems
- - Energy harvesting powered systems
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