55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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Ultra-compact Single-Channel JPEG 2000 decoder
The Single-Channel JPEG 2000 decoder IP core is an ultra-compact JPEG2000 hardware decoder optimized for single-channel HD and DCI video applications.
The IP core is optimized for silicon cost and is able to decode 720p30/60, 1080i and 1080p30/60, 2K@24fps, 2K@48fps, 2K3D@24fps, on single entry-level FPGA solutions.
The ultra-compact JPEG2000 decoder is mapped on the smallest FPGA devices such as Artix7 from Xilinx or Cyclone5 from Altera.
We provide extensive systems integration and design services and integrate a wide range of IP cores like HDMI, Ethernet MACs, JPEG 2000, crypto and high-performance memory controllers.
The IP core is optimized for silicon cost and is able to decode 720p30/60, 1080i and 1080p30/60, 2K@24fps, 2K@48fps, 2K3D@24fps, on single entry-level FPGA solutions.
The ultra-compact JPEG2000 decoder is mapped on the smallest FPGA devices such as Artix7 from Xilinx or Cyclone5 from Altera.
We provide extensive systems integration and design services and integrate a wide range of IP cores like HDMI, Ethernet MACs, JPEG 2000, crypto and high-performance memory controllers.
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JPEG 2000 decoder IP
- JPEG 2000 decoder for high-speed applications (up to multi-channel DCI 2K and 4K, HD 1080i and 1080p)
- Multi-purpose and flexible JPEG 2000 decoder
- JPEG 2000 encoder for high-speed applications (up to multi-channel DCI 2K and 4K, HD 1080i and 1080p)
- "DCI" 4K JPEG 2000 Encoder/JPEG 2000 Decoder
- 4K Mathematically Lossless JPEG 2000 Encoder/JPEG 2000 decoder
- "Beyond DCI" 2K JPEG 2000 Encoder/JPEG 2000 Decoder