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Ultra Compact 32-bit RISC-V CPU Core
AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require low energy consumption and small area. It is compliant to RISC-V technology with several efficient performance features, including simple dynamic branch prediction, instruction cache, and local memories. It supports 32 or 16 general purpose registers (GPRs) and fast or small multiplier for performance/area tradeoff. In addition, it comes with rich optional features to ease SoC integration such as vectored CLIC and PLIC for design flexibility, AHB-Lite 32-bit bus for system integration, Fast I/O interface for low latency accesses, APB for CPU local peripherals, PowerBrake and WFI/WFE mode for low power and power management, and JTAG debug interface for development support.
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Block Diagram of the Ultra Compact 32-bit RISC-V CPU Core
32-bit CPU IP
- Low power 32-bit processor supporting single precision floating point in hardware
- Scalable & Royalty-Free 32-bit CPU
- Compact High-Speed 32-bit CPU for Real-time and Linux Applications
- Compact High-Speed 32-bit CPU Core
- Compact High-Speed 32-bit CPU Core with DSP
- Compact High-Speed 32-bit CPU Core with MemBoost and PMA