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UDP/IP Ethernet IP Core
Enclustra's UDP/IP Ethernet IP core easily enables FPGA-based subsystems to communicate with other subsystems via Ethernet, using the UDP protocol. The IP core is highly configurable and optimally implemented for the use in current Altera® and Xilinx® FPGA architectures. It provides a simple to use interface to the user logic, and supports the common media independent interfaces MII, RMII, GMII and RGMII. With its 8-bit wide transmit and receive interfaces running at 125 MHz, the IP core is able to operate at full 1 Gbit/sec wire speed. 100 Mbit/sec and 10 Mbit/sec operation is also supported.
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Block Diagram of the UDP/IP Ethernet IP Core
Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E, N2P)
- 112G Ethernet PHY in TSMC (N7, N6, N5, N3P)
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency