Type-C PHY

Innosilicon Type-C IP is composed of the physical layer and the PHY logic. The physical layer contains 4 data channels, an AUX channel and bias circuit. The data channel consists of termination, equalizer and CDR circuit.
In each data channel, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The equalizer firstly changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. Then the input signals are reshaped by equalizer for frequency compensation. Finally, the serial stream is recovered by CDR and converted to 10-bit parallel output.
The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status, between a transmitter and a receiver device. The bias circuit generates voltage and current reference.
The PHY logic receives the recovered parallel data and clock signals of 4 data channels. These data are synchronized to the same clock and aligned to eliminate the channel skew. Then they are converted to 40-bit parallel data and output to the controller for further process.

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