1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
查看 Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k 详细介绍:
- 查看 Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k 完整数据手册
- 联系 Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k 供应商
Register File IP
- Ultra High-Speed Cache Memory Compiler
- 1-Port Register File Compiler GF22FDX Low Power
- Tuneable multi-port register file architecture
- TSMC CLN6FF Asynchronous Read Two Port Register File Compiler
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k