1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
Tuneable multi-port register file architecture
As wearable devices integrate increasing AI capabilities to enrich the user experience and provide product differentiation, ever more memory will be needed to support the computing demands driving up the overall power budget. Cutting and optimising power usage is critical to extending recharge windows and delivering a competitive product. As part of the system logic needed to deliver the computational capability register files are ubiquitous small blocks of memory providing either interim storage for calculations or interfacing between blocks in different clock domains. Typically, more efficient than flip-flop based register storage the standard bit cell based implementation is performance limited when developers look to move outside the typical operating norms. Multiple read/write ports, wide operating voltages and extremely high performance needs often drive designers back to power hungry flip-flops. MiniMiser elegantly addresses these challenges with dramatic power and area savings.
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register file IP
- Ultra High-Speed Cache Memory Compiler
- 1-Port Register File Compiler GF22FDX Low Power
- TSMC CLN6FF Asynchronous Read Two Port Register File Compiler
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - compiler range up to 40 k