MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
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TSMC N7FF 25.78125Gbps Enterprise SerDes
The receiver equalizes and recovers incoming serial data and de-serializes the data stream into selectable 32/40/64 bit-wide data bus. The transmitter, similarly, serializes selectable 32/40/64 bit-wide data bus and drives the serialized data off-chip with built-in adjustable de-emphasis (FFE). SerDes includes the physical media attachment layer (PMA) which is implemented as a hard macro and the physical coding sub-layer (PCS) which may be licensed separately through GUC or its 3rd party partners.
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SER IP
- IGASERT08A, Derivative IP of IGPSERT12A Lane-based 1 - 12.5 Gbps Enterprise Multi-Standard SerDes
- TSMC 12FFC Lane-based 1.25 - 22.5 Gbps Enterprise Multi-Standard SerDes
- TSMC CLN12FFC Lane-based 1.5 - 16 Gbps Enterprise Multi-Standard SerDes
- TSMC CLN28HPC+ Derivative IP of IGASERT06A Enterprise Multi-Standard SerDes
- TSMC CLN7FF Lane-based 1.5 – 22.5 Gbps Enterprise Multi-Standard SerDes
- 10G/25GBASE-R PCS+KR4 FEC IP Core