IGMTLSX04A is a synchronous LVT / ULVT periphery high-density pre-search and pipeline ternary content addressable memory (TCAM) with column redundancy feature. It is developed with TSMC 7nm 0.75V/1.8V CMOS LOGIC FinFET Process. Different combinations of words and bits can be used to generate the most desirable configurations. The pre-search scheme is built to reduce average power of Compare operation. Pipeline scheme reduces the cycle time and the access time of Compare and Read operations.
Given the desired size and timing constraints, the IGMTLSX04A compiler is capable of providing suitable synchronous TCAM instances models within minutes. It is capable of automatically generating the data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length can be neglected as long as the setup/hold times and minimum high/low pulse widths are satisfied. This allows a more flexible clock falling edge during each operation.