You are here:
TSMC CLN65LP 65nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values.
查看 TSMC CLN65LP 65nm Clock Generator PLL - 60MHz-300MHz 详细介绍：
- 查看 TSMC CLN65LP 65nm Clock Generator PLL - 60MHz-300MHz 完整数据手册
- 联系 TSMC CLN65LP 65nm Clock Generator PLL - 60MHz-300MHz 供应商
Clock Generator PLL IP
- TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
- TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
- TSMC CLN28HPC 28nm Clock Generator PLL - 700MHz-3500MHz
- TSMC CLN28HPC 28nm Clock Generator PLL - 350MHz-1750MHz
- TSMC CLN28HPC 28nm Clock Generator PLL - 175MHz-875MHz
- TSMC CLN16FFCLL 16nm Clock Generator PLL - 800MHz-4000MHz