Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
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TSMC CLN65GP 65nm Multi Phase DLL - 260MHz-1300MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance over a wide frequency range. The analog delay-line architecture used in our DLL design is internally isolated from supply noise for very low output jitter. The analog delay line also provides duty cyle correction.
特色
- Designed for high-speed interface applications.
- Generates precise multi-phase clocks directly from the reference clock.
- Delivers optimal jitter performance over a wide frequency range.
可交付内容
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
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