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TSMC CLN5FF GLink 2.0 Die-to-Die PHY
IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL interconnect and Chip-on-Wafer-on-Substrate (CoWoS®) with silicon interposer. IGPD2DY01A contains 32 TX lanes and 32 RX lanes per slice and supports 8 slices in one PHY. Each TX/RX lane can support up to 16 Gbps data rate. In summary, IGPD2DY01A offers a full-duplex data transmission with extremely low power and up to 512 Gbps data rate per slice in both directions.
Each TX/RX slice contains PMA and PCS modules. PMA supports serialization, de-serialization, data transmission, eye training, and lane repair functions. PCS provides data bus inversion, CRC/Parity check, and FIFO functions. One PLL is also included in IGPD2DY01A to generate an 8 GHz high-speed clock for data transmission.
IGPD2DY01A is designed and fabricated in TSMC 5 nm FF CMOS process with 1.2 V analog supply voltage for PLL/PMA and 0.75 V analog/digital supply voltages. Independent low power mode for PLL and slices is available.
Each TX/RX slice contains PMA and PCS modules. PMA supports serialization, de-serialization, data transmission, eye training, and lane repair functions. PCS provides data bus inversion, CRC/Parity check, and FIFO functions. One PLL is also included in IGPD2DY01A to generate an 8 GHz high-speed clock for data transmission.
IGPD2DY01A is designed and fabricated in TSMC 5 nm FF CMOS process with 1.2 V analog supply voltage for PLL/PMA and 0.75 V analog/digital supply voltages. Independent low power mode for PLL and slices is available.
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