Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
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TSMC CLN40LP Digital Delay Lock Loop
GUC’s digital delay lock loop is a high performance DLL for flash interface applications.
IGADLLS02A is a master/slave digital type delay lock loop, which provides a fixed delay value for source synchronous system according to reference clock and delay step setting. The DLL IP includes two parts: RTL soft IP and digital delay line. The IP is mainly for source synchronous system only. Any other application could not be guaranteed by this design and users should be aware of that.
The reference clock frequency of IGADLLS02A is from 100MHz to 400MHz.
IGADLLS02A is designed in TSMC CLN40LP 1.1V/2.5V Process. The metal option is 1P4M.
IGADLLS02A is a master/slave digital type delay lock loop, which provides a fixed delay value for source synchronous system according to reference clock and delay step setting. The DLL IP includes two parts: RTL soft IP and digital delay line. The IP is mainly for source synchronous system only. Any other application could not be guaranteed by this design and users should be aware of that.
The reference clock frequency of IGADLLS02A is from 100MHz to 400MHz.
IGADLLS02A is designed in TSMC CLN40LP 1.1V/2.5V Process. The metal option is 1P4M.
特色
- CLN40LP 1.1V/2.5V Process (1P4M)
- Standard cell like layout, easy for implementation
- Reference clock frequency: 50~100MHz
- Provide multiple slave delay lines
- Slave tuning range : one reference clock period
- Provide match cell to eliminate the default delay
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