IGMTLSLV02A is a synchronous LVT periphery high-density ternary content addressable memory (TCAM). It is developed with TSMC 16 nm 0.8 V/1.8 V CMOS LOGIC FinFET Compact Process. Different combinations of words, bits can be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMTLSV02A compiler is capable of providing suitable synchronous TCAM layout instances within minutes. It is capable of automatically generating the data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length can be neglected as long as the setup/hold times and minimum high/low pulse widths are satisfied. This allows a more flexible clock falling edge during each operation.