IGADLLV02A is a master/slave digital type delay lock loop, which provides a fixed delay value for source synchronous system according to reference clock and delay step setting. IGADLLV02A includes two parts: RTL soft IP and digital delay line. The DLL IP is designed for TSMC CLN16FFC/CLN12FFC 1P4M 0.8/1.8V process. The DLL IP is mainly for source synchronous system only. Any other application could not be guaranteed by this design and users should be aware of that.
- TSMC CLN 16nm/12nm CMOS logic FINFET compact 0.8V/1.8V process with 1P4M(2xa1xd) layout.
- TSMC standard cell library : tcbn16ffcllbwp16p90
- Standard cell like layout, easy for implementation
- Reference clock frequency : 100~400MHz
- Provide multiple slave delay lines
- Slave tuning range : one reference clock period
- Provide match cell to eliminate the default delay