TSMC CLN12FFCLL 12nm Deskew PLL - 800MHz-4000MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.

• 查看 TSMC CLN12FFCLL 12nm Deskew PLL - 800MHz-4000MHz 完整数据手册
• 联系 TSMC CLN12FFCLL 12nm Deskew PLL - 800MHz-4000MHz 供应商