IGADLLM03A is a master/slave digital type delay lock loop, which provides a fixed delay value for source synchronous sys-tem according to reference clock and delay step setting. The DLL IP includes two parts: RTL soft IP and digital delay line. The IP is mainly for source synchronous system only. Any other application could not be guaranteed by this design and users should be aware of that.
- CL013G 1.2 Process (1P4M and above)
- Standard cell like layout, easy for implementation
- Reference clock frequency: 50~100MHz
- Provide multiple slave delay lines
- Slave tuning range: 1 reference clock period
- Provide match cell to eliminate the default delay
- Update function is provided to avoid the slave output glitch