MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
TSMC 40 ULP Combo voltage regulator combining a linear regulator for active mode with an ultra-low quiescent regulator for sleep mode
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Combo Regulators IP
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- TSMC 40nm ULP combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode
- TSMC 40nm ULP eFlash combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode