TSMC 12 FFC Power On Reset_POR

The ARK12FFC_POR IP belongs to a family of Power Reset (POR) circuits
POR : Power on reset circuit generates output flag signal once the power supply voltage rises above specified level.

The ARK12FFC_POR will generate a log "high" output signal from the POR18 pin when the I/O power supply voltage (AVDDH) rises above a specified level (V~TH_RISE_IO~) or generate a log "high" output signal from the POR_CORE pin when the CORE power supply voltage (DVDD) rises above a specified level (V~TH_RISE_CORE~). And the cell will generate a logic “low” output signal from the POR18 pin when the I/O power supply voltage(AVDDH) drops  below another specified level(V~TH_FALL_IO~) which specified by parameter as hysteresis(V~TH_HYS_IO~) or generate a logic “low” output signal from the POR_CORE pin when the CORE power supply voltage(DVDD) drops  below another specified level(V~TH_FALL_CORE~) which specified by parameter as hysteresis(V~TH_HYS_CORE~)

The  ARKT12FFC_POR IP solutions for integration on SoC. It is specified from –40°C to +125 °C.

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