Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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Tiny UART
Small is beautiful...
The DμART is one of the tiniest UART IP Cores available on the market.The DμART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of the transfer operations performed by the UART, as well as any error conditions (overrun, framing). The DμART includes a programmable baud rate generator capable of dividing timing reference clock input by divisors of 1 to (216-1), and producing 16 × clock for driving internal transmitter logic. Provisions are also included to use this 16 × clock to drive receiver logic. The DμART has a processor-interrupt system. Interrupts can be programmed to user's requirements, minimizing computing required to handle the communications link.
The core is perfect for applications where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices.
The DμART is one of the tiniest UART IP Cores available on the market.The DμART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of the transfer operations performed by the UART, as well as any error conditions (overrun, framing). The DμART includes a programmable baud rate generator capable of dividing timing reference clock input by divisors of 1 to (216-1), and producing 16 × clock for driving internal transmitter logic. Provisions are also included to use this 16 × clock to drive receiver logic. The DμART has a processor-interrupt system. Interrupts can be programmed to user's requirements, minimizing computing required to handle the communications link.
The core is perfect for applications where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices.
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Block Diagram of the Tiny UART
