5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+
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Tensilica AI Boost
The Cadence® Tensilica® NNE 110 offers an energy-efficient hardware-based solution that has an AI accelerator of smaller footpri
The product architecture natively supports the most common network layers found in these applications including convolution, depth-wise separable convolution, fully connected, LSTM, pooling, reshaping, and concatenation layers. Other layers can be support
The product architecture natively supports the most common network layers found in these applications including convolution, depth-wise separable convolution, fully connected, LSTM, pooling, reshaping, and concatenation layers. Other layers can be support
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Block Diagram of the Tensilica AI Boost
AI boost IP
- NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
- RISC-V Tensor Unit
- 64-bit CPU with RISC-V Vector Extension
- 64-bit CPU with RISC-V Vector Extension
- High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP
- High performance dual-issue, out-of-order, 7-stage pipeline superscalar core