TBI to EPCS Bridge on G4 (full SIPDP)

The CoreTBItoEPCS IP Core is a bridge that appears between the Ten-Bit Interface (TBI) and External PCS (EPCS). The Core supports Ten-Bit interface Rx/Tx data bus on TBI side and 20-bit Rx/Tx data bus on EPCS side. This block receive TBI data (with double data rate) and transmit on EPCS bus and vice-versa. CoreTBItoEPCS includes user testbench for verification.

• 查看 TBI to EPCS Bridge on G4 (full SIPDP) 完整数据手册
• 联系 TBI to EPCS Bridge on G4 (full SIPDP) 供应商