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Synthesizable 68000 Compatible CPU Core
The V68000 is a synthesizable VHDL (soft) core design which is object code compatible with Motorola's popular MC68000. The V68000 is intended to be used in system-on-a-chip applications constructed using gate-arrays or standard cells. It should be especially interesting to designers who currently use MC68000s in embedded control applications and want to integrate its functionality with other designs/peripherals/etc. onto a single chip (ASIC).
The V68000 is a fully synchronous design and contains no microcode; all control is implemented via state machines. It is written in synthesizable VHDL using IEEE standard libraries. It uses a single clock. The design has also been translated to Verilog.
The V68000 core interfaces to other on-chip periperals and memory using simple, synchronous interface. A "ring" circuit is available that converts the synchronous interface into a bus that closely resembles the MC68000 (Motorola) bus.
The V68000 has very good performance, with many instructions completing in 2 to 4 clock cycles (using 0 wait state memory). Most instructions use fewer clock cycles than the original MC68000.
The V68000 also contains debug assist hardware to provide "ICE"-like debugging access. This hardware is intended to be accessed through a JTAG port (a JTAG interface is also available).
The V68000 synthesizes to approximately 30 to 35 Kgates (this is very dependent upon the target libary) when using a typical standard cell libary. Version 3.0 of the design is currently in the test/validation process. It makes slightly different tradeoffs to allow better optimization in an FPGA environment. The design goal for this version is operation at 80 to 100 Mhz in an Altera FPGA device.
The design kit includes the synthesizable VHDL model, a sample synthesis script, a sample constraint file, a VHDL test bench, and test stimulus files. Over 2600 test sequences are included to validate instruction and address mode functionality. Instructions and a build script are also included to create a software generation environment for embedded systems using the GNU gcc tools.
VLSI Concepts can provide customization of the design, if requested.
Design and integration assistance is also available from VLSI Concepts.
The V68000 is a fully synchronous design and contains no microcode; all control is implemented via state machines. It is written in synthesizable VHDL using IEEE standard libraries. It uses a single clock. The design has also been translated to Verilog.
The V68000 core interfaces to other on-chip periperals and memory using simple, synchronous interface. A "ring" circuit is available that converts the synchronous interface into a bus that closely resembles the MC68000 (Motorola) bus.
The V68000 has very good performance, with many instructions completing in 2 to 4 clock cycles (using 0 wait state memory). Most instructions use fewer clock cycles than the original MC68000.
The V68000 also contains debug assist hardware to provide "ICE"-like debugging access. This hardware is intended to be accessed through a JTAG port (a JTAG interface is also available).
The V68000 synthesizes to approximately 30 to 35 Kgates (this is very dependent upon the target libary) when using a typical standard cell libary. Version 3.0 of the design is currently in the test/validation process. It makes slightly different tradeoffs to allow better optimization in an FPGA environment. The design goal for this version is operation at 80 to 100 Mhz in an Altera FPGA device.
The design kit includes the synthesizable VHDL model, a sample synthesis script, a sample constraint file, a VHDL test bench, and test stimulus files. Over 2600 test sequences are included to validate instruction and address mode functionality. Instructions and a build script are also included to create a software generation environment for embedded systems using the GNU gcc tools.
VLSI Concepts can provide customization of the design, if requested.
Design and integration assistance is also available from VLSI Concepts.
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