Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
subLVDS IO Pad Set
特色
- Input receive sensitivity of 50mV peak differential (without hysteresis)
- Common mode range from 0.4V to 1.8V (limited by power supply)
- Powered by 1.8V I/O and 1.1V core supplies
- Power consumption: 4.94 mW max @ 600 MHz
可交付内容
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
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