You are here:
Streaming Multi-port SDRAM Memory Controller IP Core
The Streaming Multi-port SDRAM Memory Controller IP Core provides a native RD or WR local port bus interface to SDRAM memory. The core integrates: a burst memory controller core, a port arbitrator and intelligent look-ahead FIFO controller into one easy-to-use core. It supports SDR, DDR, DDR2 and Mobile DDR memory devices in a single IP Core assuring designers of a smooth low-risk migration path with changing SDRAM technology.
The Streaming Multi-port SDRAM Memory Controller IP Core supports up to ten independently clocked streaming data sources operating from one shared high-bandwidth memory system.
The Streaming Multi-port SDRAM Memory Controller IP Core supports up to ten independently clocked streaming data sources operating from one shared high-bandwidth memory system.
查看 Streaming Multi-port SDRAM Memory Controller 详细介绍:
- 查看 Streaming Multi-port SDRAM Memory Controller 完整数据手册
- 联系 Streaming Multi-port SDRAM Memory Controller 供应商
Block Diagram of the Streaming Multi-port SDRAM Memory Controller
