DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
Stream Buffer Controller
The IP core is highly configurable in terms of operation mode, buffer size and buffer address for each stream. The configuration is done over a memory mapped slave interface, either by an embedded-CPU, by a FPGA Manager application or by an application specific stream configurator controller in VHDL.
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Block Diagram of the Stream Buffer Controller
![Stream Buffer Controller Block Diagam](http://www.design-reuse.com/sip/blockdiagram/46331/20190409112139-main-stream_buffer_controller_overview_540.png)
Stream Buffer Controller IP
- Stream Buffer Controller
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface
- MIPI CSI-2 TX Controller for v2.1