Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
You are here:
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library.
查看 Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process 详细介绍：
- 查看 Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process 完整数据手册
- 联系 Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process 供应商