USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 12-Track high speed Generic Core Cell Library (C50).
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