MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
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Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/HVT process 12-Track Standard Cell Library (C35).
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