MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
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Standard Cell (Generic) Library IP, 9 tracks, UMC 0.35um Logic process
UMC 0.35um 3.3V Logic process Standard Cell Library.
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