Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
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Standard Cell (ECO) Library IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Metal1 Start ECO Core Cell Library (for FSR0H_M).
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