MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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Standard Cell (ECO) Library IP, HVT, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process ECO_M1 Core Cell Library.
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