MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
Sprite Drawing IP core
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Sprite Drawing IP core IP
- High-performance 2D (sprite graphics) GPU IP combining high pixel processing capacity and minimum gate count.
- BitBLT Graphics Hardware Accelerator (AXI Bus)
- BitBLT Graphics Hardware Accelerator (AHB Bus)
- BitBLT Graphics Hardware Accelerator (AXI4 Bus)
- 2D (vector graphics) GPU IP Further advanced architecture for minimized CPU load and increased pixel performance in vector processing
- Shader architecture type 3D GPU Integrating the OpenVG 1.1 hardware processing pipeline