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SPI Master/Slave- Serial Peripheral Interface
The SPI core is a fully configurable SPI master/slave
device, which allows user to configure polarity and phase of a serial clock signal (SCK). It allows the microcontroller to communicate with serial peripheral devices and is also capable of interprocessor communications in a multi-master system. A
serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines. DSPI data is simultaneously transmitted and received. What's the most important, it's a technology independent design, that can be implemented in a variety of process technologies.
The SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. It can be configured as a master or a slave device, with data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the core is configured as a master, the software selects one of eight different bit rates for the serial clock. The core automatically
drives selected by SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and address SPI slave device, to exchange serially shifted data. An error-detection logic is included, to support interprocessor communications. A write collision detector indicates, when an attempt is made to write
data to the serial shift register, while transfer is in progress. A multiple-master mode-fault detector automatically disables the SPI output drivers, if more than one SPI devices simultaneously attempts to become a bus master. The core is fully customizable and can be tailored to your configuration and requirements. It includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.
for more info, welcome contact us :sales(at)wwago-inc.com
device, which allows user to configure polarity and phase of a serial clock signal (SCK). It allows the microcontroller to communicate with serial peripheral devices and is also capable of interprocessor communications in a multi-master system. A
serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines. DSPI data is simultaneously transmitted and received. What's the most important, it's a technology independent design, that can be implemented in a variety of process technologies.
The SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. It can be configured as a master or a slave device, with data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the core is configured as a master, the software selects one of eight different bit rates for the serial clock. The core automatically
drives selected by SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and address SPI slave device, to exchange serially shifted data. An error-detection logic is included, to support interprocessor communications. A write collision detector indicates, when an attempt is made to write
data to the serial shift register, while transfer is in progress. A multiple-master mode-fault detector automatically disables the SPI output drivers, if more than one SPI devices simultaneously attempts to become a bus master. The core is fully customizable and can be tailored to your configuration and requirements. It includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.
for more info, welcome contact us :sales(at)wwago-inc.com
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