MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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Specialty PCI IO IP, UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process 2.5VOD3.3V PCI-X IO Cell Library.
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