MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process 2.5VOD3.3V PCI-X BOAC IO Cell Library.
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