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Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain, SPI in TSMC 110nm
This silicon proven, wirebond and flipchip compatible library is particularly tailored to address gaps in the native foundry IO offerings for this node. It features a 1.2V/3.3V GPIO with selectable drive strengths and optional internal 100K ohm pull up or pull down resistor and a selectable Schmitt trigger. The ODIO mode targets the official I2C standard at 3.3V. Cells for IO core power and ground with built in ESD are included. Thelibrary is enriched with feed through, filler, corner, and domain break cells to allow for flexible padring constructions. ESD design levels are 2kV HBM and 500V CDM.
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