The Xelic SONET/SDH Transport Processor Core (XCS192F) performs transport overhead processing, aligns incoming SONET/SDH frames and provides overhead interpretation with error detection and performance monitoring. The XCS192F contains independent transmit and receive processors with dedicated external ports for overhead insertion and extraction. Incoming/outgoing data is transferred at an STS-192/STM-64 rate using a 64-bit data bus operating at 155.52Mb/s. NOTE: This core implements a data valid scheme to allow for operation at clock speeds above the 155.52Mb/s line rate.
The XCS192F Transmit Processor inserts transport overhead, calculates and inserts B1/B2 parity (with corruption capability), automatically generates line RDI, and scrambles (with corruption capability) SONET/SDH frames. A programmable trace buffer is implemented for 1 byte, 16 byte or 64 byte trace message insertion. Diagnostics support includes optional corruption of inserted parity, corruption of scrambling, framing corruption, and programmable generation of line AIS, and line RDI conditions.
The XCS192F Receive Processor contains a configurable frame alignment unit with programmable options for OOF and LOF algorithm state transitions. Incoming frames are descrambled (optional) and aligned for transport overhead processing. Transport overhead information is extracted to internal register locations and dedicated section DCC, line DCC, section order wire, line order wire, and transport overhead external ports. Transport overhead interpreters are implemented to detect and report various conditions which include LOS, LOF, LOA, OOF, B1 error, SD, SF, B2 error, AIS-L, and RDI-L errors with optional maskable interrupt generation provided. LOS detection is available through either an incoming signal or an internal programmable LOS detection algorithm. Section Trace messages of 16 or 64 byte lengths are evaluated for trace identifier mismatch (TIM) and trace identifier unstable (TIU) conditions. Line AIS is inserted through programmable internal register control. Diagnostics support includes optional corruption of calculated parity, corruption of descrambling, and Line AIS generation.
Performance counters (configurable for bit or block count type) are provided for the accumulation of detected OOF, B1 parity, B2 parity and REI errors for incoming SONET/SDH frames. B2 parity errors are accumulated with programmable threshold capability for signal degrade (SD) and signal fail (SF) detection. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCS192F provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCS192F core available under flexible single use licensing terms with netlist or source code deliverables.
- Implements flexible data bus architecture.
- Provides for bypass and normal (transport overhead processing) modes of operation.
- Implements 16-bit register interface for programming of internal registers.
- Compliant with ITU-T G.707 and Telcordia GR-253-CORE Specifications.
- Inserts transport overhead through internal register programming and/or external overhead ports.
- Supports auto generated or synchronized frame start generation.
- Provides transmit facility and terminal loopback options for diagnostic purposes.
- Supports transport overhead insertion through dedicated external section DCC, line DCC, section order wire, line order wire, and transport overhead ports.
- Allows for blanking of all transport overhead locations except H1/H2/H3 bytes.
- Supports optional SONET/SDH frame scrambling with programmable scrambler corruption capability for diagnostic purposes.
- Provides automatic REI insertion for B2 parity errors detected in the XCS192F Receive Processor.
- Allows for the insertion of programmable 1, 16 or 64 byte trace messages.
- Supports legacy J0/Z0 insertion.
- Calculates and inserts B1/B2 parity information with optional corruption capability.
- Provides programmable internal registers for the insertion of selected transport overhead byte locations.
- Allows for programmable automatic insertion of line RDI for the detection (XCS192F Receive Processor) of Loss of Signal (LOS), Loss of Frame (LOF), Loss of Alignment (LOA), Out of Frame (OOF), Alarm Indication Signal (AIS), Remote Defect Indication (RDI), Signal Fail (SF), Signal Degrade (SD), Trace Identifier Mismatch (TIM), or Trace Identifier Unstable (TIU) conditions.
- Supports programmable insertion of line AIS.
- Provides extended programmable diagnostics capability to force line AIS, LOS, RDI, and frame corruption insertion.
- Provides flexible frame alignment capability with programmable options for OOF and LOF algorithm state transitions. Diagnostic capability is provided to force LOF and OOF state conditions.
- Extracts transport overhead to internal register locations and dedicated external ports for section DCC, line DCC, section order wire, line order wire, and transport overhead.
- Provides receive facility and terminal loopback options for diagnostic purposes.
- Supports optional SONET/SDH frame descrambling with programmable descrambler corruption capability for diagnostic purposes.
- Supports the programmable insertion of Line AIS frames. Diagnostic capability is provided to force a line AIS condition.
- Provides independent 16-bit saturating performance counters (configurable for bit or block type) for the accumulation of OOF and B1 errors with programmable latch and clear or incoming error sync capture options. Supports optional interrupt generation for OOF and B1 error detection.
- Provides a 32-bit saturating performance counter (configurable for bit or block type) for the accumulation of REI errors with programmable latch and clear or incoming error sync capture options. Supports optional interrupt generation for REI error detection.
- Provides a 32-bit saturating performance counter (configurable for bit or block type) for the accumulation of B2 errors with programmable threshold capability (including optional error sync update capability).
- Provides optional interrupt generation for signal degrade (SD) and signal fail (SF) detection.
- Includes optional masking capability for all interrupt condition reporting.
- Provides section trace interpreter with programmable trace accept and unstable counts for message lengths of 1, 16 or 64 bytes.
- Provides LOS detection through a selectable dedicated external input or programmable internal LOS state machine.
- Interprets and extracts F1, APS, S1 (optional byte or nibble detection) overhead information to internal register locations with programmable accept and inconsistent maskable interrupt capability.
- Detects LOS, LOF, LOA, OOF, TIM, TIU, B1 error, SD, SF, B2 error, AIS-L, and RDI-L conditions and provides optional interrupt generation.
- Calculates and compares extracted B1 and B2 parity for all incoming SONET/SDH frames.