MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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SONET/SDH OC-3 / OC-12 Transceiver/CDR PHY
Innovative architecture to meet the SDH/ Sonet Jitter Spec utilizing deep sub-micron single poly CMOS process
Fully in compliance with ANSI, Bellcore and ITU jitter Specifications
Proven in multi-port end customer SOC designs
Designed for multi- port applications using re-usable building blocks targeted for process migration/ new application domains
Innovative (patent pending) CMOS architecture to guarantee compliance with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation
Proprietary Advanced Signal Processing techniques utilized for clock recovery provides on-chip filtering : immunity to external/PCB noise problem in existing solutions
Designed for multiple integration on a single IC for System-On-Chip applications
Custom configurable width serializer-deserializer (SERDES) option
Fully in compliance with ANSI, Bellcore and ITU jitter Specifications
Proven in multi-port end customer SOC designs
Designed for multi- port applications using re-usable building blocks targeted for process migration/ new application domains
Innovative (patent pending) CMOS architecture to guarantee compliance with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation
Proprietary Advanced Signal Processing techniques utilized for clock recovery provides on-chip filtering : immunity to external/PCB noise problem in existing solutions
Designed for multiple integration on a single IC for System-On-Chip applications
Custom configurable width serializer-deserializer (SERDES) option
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