Aliathon’s SONET/SDH Framer Core implements Transport Overhead framing functions for SONET/SDH links, including frame generation and delineation, protection switching, concatenated and channelized Higher Order Path termination and defect/overhead processing. It provides a flexible, resourceefficient, FPGA based solution for interfacing to one or more SONET/SDH links, such as
- 1 x OC3/STM1,
- 8 x OC3/STM1
- and 2 x OC12/STM4,
- or 1 x OC192/STM16.
- Conforms to G.707, G.806, G.783 and T1.105
- Interfaces to the following SONET/SDH links:
- OC1/STM0, OC3/STM1, OC12/STM4, OC48/STM16, OC192/STM64
- Performs frame generation, delineation and scrambling for one or multiple links.
- Detects Loss of Signal (LOS), Out of Frame (OOF) and Loss of Frame (LOF) defects.
- Extracts Regenerator/Multiplex Overhead and detects B1 and B2 errors.
- Implements MS protection switching. Processes all STS/AU pointers and Higher Order paths.
- Detects AIS and LOP defects, and B3 BIP errors.
- All legal configurations of STS/VC sizes are supported, and may be changed dynamically.
- Full Overhead and Defect processing for all TOH and STS/VC, including:
- LOF, OOF, B1, B2, MS-AIS/RDI, MS-REI, AU-AIS/LOP and Path B3, REI, RDI. Trace Messages (J0, J1). Signal Degrade/Excessive Error detection (B2, B3). Path Labels (S1, C2). Performance Monitoring counters (B1, B2, MSREI, Path B3 and REI). Upstream/Downstream Consequent Action.