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soft eFPGA IP
SPC V2 is ADICSYS's updated eFPGA featuring the latest clocking and arithmetic functions.
Under the hood transformations allow better LUT per mm2 count and scalability to 100k's LUT arrays.
Field measurements show 4X density gain over similar blocks, matching full custom FPGA cores without a need for test silicon.
ADICSYS FPGA IP's are still 100% synthesizable with no hidden trick.
Under the hood transformations allow better LUT per mm2 count and scalability to 100k's LUT arrays.
Field measurements show 4X density gain over similar blocks, matching full custom FPGA cores without a need for test silicon.
ADICSYS FPGA IP's are still 100% synthesizable with no hidden trick.
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